1. Field of the Invention
The present invention relates to a carrier used for the transportation of semiconductor wafers from one processing station to another.
2. Description of the Related Art
FIG. 1A shows a top view and FIG. 1B shows a front view of a conventional wafer carrier. In FIG. 1B, the carrier 10 is seen on the side of an opening through which the wafers are inserted. The carrier 10 includes a base 12 from which two vertical walls 13 extend on both sides. Walls 13 comprise horizontal grooves 15 with a trapezoidal section. Each groove 15 of one of walls 13 is in the same plane as a groove 15 of the other wall 13, so that the two grooves form a single groove for receiving a wafer (not shown).
As can be seen in FIG. 1A, walls 13 include a straight portion 7 on the side of the insertion opening and a curved portion 9 at the back, which follows the shape of the wafers and stops them. The carrier 10 is generally provided with a handle 17 forming integral with the upper surface of the carrier 10, arranged close to the insertion opening 11.
These carriers are used to carry batches of wafers, stacked vertically in the carrier 10, from one processing station to another. At each station, the wafers are loaded and unloaded one by one by means of a handling robot provided with fingers which have to slide between the wafers. For the robot to be able to properly handle the wafers, it is necessary that the wafer positions vary little with respect to corresponding reference positions. The accuracy of the wafer positioning depends on grooves 15.
FIG. 2 shows an enlarged view of a groove 15. As mentioned previously, this groove 15 conventionally forms a trapezoidal shape, the narrowest side of the trapezoid forming the bottom 17 of the groove 15. This shape enables an easy handling of the wafers with no clamping risk. The upper wall and the lower wall of the groove are slanted symmetrically with respect to the horizontal direction.
FIG. 2 also shows a same wafer 20 such as it is normally arranged at the level of straight portion 7 of the groove 15 and at the level of curved portion 9 of the groove 15 (see FIG. 1A). These two positions are designated by A and B, respectively.
The fully inserted position is position B. In this position B, the edge of the wafer 20 is generally in contact with the bottom 17 of groove 15, this being due to the fact that, during transportation, the carriers are arranged with their insertion opening 11 facing upwards and that these carriers are then handled with care when they are placed vertically, to avoid ejecting the wafers.
The load and unload position is position A. In position A, the side of the wafer 20 closest to the insertion opening 11 slants downward. This downward slanting of wafer 20 is due to the slanting of the lower wall of the groove 15. The distance between the edges of two or more stacked wafers 20 in carrier 10, in the load/unload position A is not uniform. Non-uniform distances reduce the operation range of the handling robots and increase risks of wafer damage.
To address this problem of slanting, carrier manufacturers have devised several solutions to ensure that wafers 20 are maintained more horizontally. The manufacturer, FLUOROWARE has provided wafer carriers in which the groove walls, still slanted, comprise a horizontal portion in the vicinity of the groove bottom.
This solution, however, has the disadvantage of widening the groove bottom, which decreases the axial positioning accuracy ofthe wafers when placed vertically. This inaccuracy is incompatible with an operation of wafer transfer to special carriers comprising, in the same volumes, twice as many wafers. Indeed, this automatic transfer operation between carriers is performed by lifting the wafers by means of a comb. If the wafers are axially mispositioned, they could be mishandled and damaged by the comb.
In another solution to address this problem of slanting, the manufacturer EMPAK has devised to form, in the bottom of the grooves 15 at the curved portion 9, humps on the slanted walls. The humps aim at pushing the rear edges of the wafers substantially to the position of the edges in straight portion 7 of the grooves 15.
This solution has the disadvantage of being difficult to manufacture. Specifically, it is difficult to form these humps with a sufficient accuracy and to ensure that the rear edges of the wafers are always pushed by the same distance, which causes wafer slanting dispersions.
Accordingly, a need exists to provide a wafer carrier that minimizes the problem of wafer slanting without these shortcomings.